APRÈN. Portal de la producció docent del professorat de la UPC

This thesis explores the implementation of reservoir computing networks in real-time spiking neural network (SNN) hardware, using the Hardware Emulator of Evolving Neural Systems (HEENS) platform. The study aims to leverage the efficiency of SNNs for real-time tasks such as digit classification. A carefully configured SNN architecture was designed on HEENS, focusing on key parameters like synaptic connectivity ratios and neuron dynamics to optimize performance. Initial tests validated the system's functionality, followed by further experiments to enhance classification accuracy using Ridge Regression for the readout layer. The results demonstrate the potential of reservoir computing in hardware-based neuromorphic systems, offering promising applications in real-time, energy-efficient computing.

The presented thesis proposes to explore the implementation of different neural appli- cations, in particular, the Adaptive Exponential Integrate and Fire (aEIF) neural model on a neuromorphic device called HEENS, and a simulation of a Spiking Neural Network with a Reservoir topology, along with the comparison of the results with an analogue neural counterpart, implemented in CMOS technology. For doing so, initially, some basic concepts about neuron?s modeling and Spiking Neural Network are exposed, and then HEENS multiprocessor is introduced, both in the architecture and its software support. Afterwards, the focus is moved toward four different spiking neural models, explaining some theory and their equations, and for one of them, also the HEENS implementation. Lastly, a comparison between an analogue and a digital technologies implementing the same model over a reservoir network topology is discussed, presenting similarities and differences of the two approaches.

This thesis has focused on introducing a multi node functionality on a spiking neural processor (HEENSMB) while maintaining the newly added features of the HEENS OneBoard system as well as keeping the array size as large as possible. In order to introduce the multi node functionality, the system has been enhanced to be able to reset all nodes and ensure a synchronous start, aiding in the scalability of the HEENS architecture and introducing a simple way of resynchronizing the entire system. In order to facilitate scalability within the HEENS architecture, the ID?s used and ring size are made configurable. The configuration of the program instructions and synapses can be loaded onto the system through the master node, which will then distribute it to all slave nodes, allowing easy reconfiguration within seconds. Synchronization during the emulation cycle is controlled by the master node and followed by all slave nodes. Through a second finish packet at the end of the distribution phase, it is ensured that all slaves stay in sync. Next to this, it is now possible to monitor up to four neuron potentials of any four neurons within the entire ring, while having a 9x16 array size (times 8 total layers) for a total of 1152 neurons per node. It is not required for any node to have the same array size as the master. The new HEENS-MB architecture described in VHDL has been implemented and verified using simulations in Questasim Advanced Simulator tool using three nodes and has been tested with two AMD Zync 7000 SoC ZC706 Evaluation boards. The evaluation boards have been connected with each other in a loop using the high-speed GTX interface and tested using four different neural networks. The networks used the LIF neural model, able to use global synapses (board-to-board connections). Overall, the Multi-node address event ring communication system implemented in the HEENS-MB architecture is fully functional now and can be expanded to also support Kintex family FPGA devices in order to create larger neural networks. In addition, further work can be done in the expansion of the HDMI display in order to display more than 1000 neurons and the system could be expanded with the logging capability for neuron potentials.

Artificial Neural Networks (ANNs) are powerful computational tools that are used to solve complex pattern recognition, function estimation and classification problems not manageable by other analytical tools. They are inspired by the structure and function of the human brain and throughout their development, they have been evolving towards more powerful and more biologically realistic models. A new generation of ANNs: Spiking Neural Networks (SNNs) have been developed. These networks emulate the neurobiological processing of information with temporal dynamics and precise timing. They are energy efficient and amenable to hardware application development. Such hardware SNNs work in real time and thus, having a real-time display makes full sense. This current thesis presents the realization of a real-time display using High-Definition Multimedia Interface (HDMI) connected to an ongoing project. This project uses HEENS (Hardware Emulator of Evolved Neural System) architecture to implement hardware SNNs on Zynq FPGAs (Field Programmable Gate Arrays). First of all, the communication to HDMI has been established, on two boards ZedBoard and Zynq ZC706. Screen resolution, video timings and color format have been studied. I2C (Inter-Integrated Circuit) communication has been examined and especially with the slave ADV7511, the HDMI transmitter, whose documentation has been also studied thoroughly. This transmitter has to be configured via I2C to be able to receive the HDMI signals and transmit them to the connector. Finally, all this acquired knowledge has enabled the actual implementation on the boards using VHDL (VHSIC (Very High Speed Integrated Circuit) Hardware Description Language) of the HDMI connection. As a result, bands of colors can be shown on monitor displays. Then, the representation of the Spiking Neural Network behavior has been made on screen, with plots to display the evolution in real time of the network. Communication has been established between the actual project architecture and the real-time display in order to receive the neural information and store it in a form which will allow their plot. At the same time, text generation has been implemented to be able to write text on screen. VHDL code has been developed to generate the plots with contours, ticks and labels as any standard chart. The first plot that has been made is the raster plot of the neuron spikes over time. Next, in order to monitor furthermore the Spiking Neural Network, another plot has been implemented to display internal neural parameters. Among these analog parameters, one of the most important is the membrane potential, whose plot has been studied more specifically. In the end, both plots: the raster plot and the membrane potential plot (for four chosen neurons to monitor), are displayed at the same time on the screen. To conclude, HDMI communication has been established on FPGA in order to monitor a Spiking Neural Network in real time. Two plots are displayed on the screen: the spikes over time and neural parameters for a few selected neurons of the network.